rev. 0.1 / dec 2008 1 240pin ddr3 sdra m unbuffered dimms ** contents are subject to ch ange without prior notice. ddr3 sdram unbuffered dimms based on 1gb a version hmt164u6afp(r)6c hmt112u6afp(r)8c hmt112u7afp(r)8c hmt125u6afp(r)8c hmt125u7afp(r)8c
rev. 0.1 / dec 2008 2 hmt164u6afp(r)6c hmt112u6(7)afp(r)8c hmt125u6(7)afp(r)8c revision history revision no. history draft date remark 0.01 initial draft for internal review nov. 2007 preliminary 0.02 added idd & halogen-free products mar. 2008 preliminary 0.1 initial specification release. corrected typo on package ball feature. dec 2008
rev. 0.1 / dec 2008 3 hmt164u6afp(r)6c hmt112u6(7)afp(r)8c hmt125u6(7)afp(r)8c table of contents 1. description 1.1 device features and ordering information 1.1.1 features 1.1.2 ordering information 1.2 speed grade & key parameters 1.3 address table 2. pin architecture 2.1 pin definition 2.2 input/output functional description 2.3 pin assignment 3. functional block diagram 3.1 512mb, 64mx64 module(1rank of x16) 3.2 1gb, 128mx64 module(1rank of x8) 3.3 1gb, 128mx72 ecc module(1rank of x8) 3.4 2gb, 256mx64 module(2rank of x8) 3.5 2gb, 256mx72 ecc module(2rank of x8) 4. address mirroring feature 4.1 dram pin wiring for mirroring 5. absolute maximum ratings 5.1 absolute maximum dc ratings 5.2 operating temperature range 6. ac & dc operating conditions 6.1 recommended dc operating conditions 6.2 dc & ac logic input levels 6.2.1 for single-ended signals 6.2.2 for differential signals 6.2.3 differential input cross point 6.3 slew rate definition 6.3.1 for ended input signals 6.3.2 for differential input signals 6.4 dc & ac output buffer levels 6.4.1 single ended dc & ac output levels 6.4.2 differential dc & ac output levels 6.4.3 single ended output slew rate 6.4.4 differential ended output slew rate 6.5 overshoot/undershoot specification 6.6 input/output capacitance & ac parametrics 6.7 idd specifications & measurement conditions 7. electrical characteristics and ac timing 7.1 refresh parameters by device density 7.2 ddr3 standard speed bins and ac para 8. dimm outline diagram 8.1 512mb, 64mx64 module(1rankx16) 8.2 1gb, 128mx64 module(1rank of x8) 8.3 1gb, 128mx72 ecc module(1rank of x8) 8.4 2gb, 256mx64 module(2rank of x8) 8.5 2gb, 256mx72 ecc module(2rank of x8)
rev. 0.1 / dec 2008 4 hmt164u6afp(r)6c hmt112u6(7)afp(r)8c hmt125u6(7)afp(r)8c 1. description this hynix unbuffered dual in -line memory module(dimm) series consists of 1gb a version. ddr3 sdrams in fine ball grid array(fbga) packages on a 240 pin glass-epoxy su bstrate. this ddr3 unbuffered dimm series based on 1gb a ver. provide a high performance 8 byte interface in 133.35mm width form factor of industry standard. it is suitable for easy interchange and addition. 1.1 device features & ordering information 1.1.1 features ? vdd=vddq=1.5v ? vddspd=3.3v to 3.6v ? fully differential clock inputs (ck, /ck) operation ? differential data strobe (dqs, /dqs) ? on chip dll align dq, dqs and /dqs transition with ck transition ? dm masks write data-in at the both rising and falling edges of the data strobe ? all addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock ? programmable cas latency 5, 6, 7, 8, 9, 10, and (11) supported ? p r o g r a m m a b l e a d d i t i v e l a t e n c y 0 , c l - 1 , a n d c l - 2 s u p ported ? programmable cas write latency (cwl) = 5, 6, 7, 8 ? programmable burst leng th 4/8 with both nibble sequential and interleave mode ? bl switch on the fly ? 8banks ? 8k refresh cycles /64ms ? ddr3 sdram package: jedec standard 78ball fbga(x4/x8), 96ball fbga(x 16) with support balls ? driver strength selected by emrs ? dynamic on die termination supported ? asynchronous reset pin supported ? zq calibration supported ? tdqs (termination data strobe) supported (x8 only) ? write levelization supported ? auto self refresh supported ? on die thermal sensor supported (jedec optional)
rev. 0.1 / dec 2008 5 hmt164u6afp(r)6c hmt112u6(7)afp(r)8c hmt125u6(7)afp(r)8c 1.1.2 ordering information part name density org. # of drams # of ranks materials ecc ts hmt164u6afp6c-s6/s5/g8/g7/h9/h8 512mb 64mx64 4 1 lead-free none no HMT164U6AFR6C-s6/s5/g8/g7/h9/h8 512mb 64mx64 4 1 halogen-free none no hmt112u6afp8c-s6/s5/g8/g7/h9/h8 1gb 128mx64 8 1 lead free none no hmt112u6afr8c-s6/s5/g8/g7/h9/h8 1gb 128mx64 8 1 halogen-free none no hmt112u7afp8c-s6/s5/g8/g7/h9/h 8 1gb 128mx72 9 1 lead free ecc yes hmt112u7afr8c-s6/s5/g8/g7/h9/h8 1gb 128mx72 9 1 halogen-free ecc yes hmt125u6afp8c-s6/s5/g8/g7/h9/h8 2gb 256mx64 16 2 lead free none no hmt125u6afr8c-s6/s5/g8/g7/h9/h8 2gb 256mx64 16 2 halogen-free none no hmt125u7afp8c-s6/s5/g8/g7/h9/h 8 2gb 256mx72 18 2 lead free ecc yes hmt125u7afr8c-s6/s5/g8/g7/h9/h8 2gb 256mx72 18 2 halogen-free ecc yes
rev. 0.1 / dec 2008 6 hmt164u6afp(r)6c hmt112u6(7)afp(r)8c hmt125u6(7)afp(r)8c 1.2 speed grade & key parameters 1.3 address table mt/s ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 unit grade -s6 -s5 -g8 -g7 -h9 -h8 -p1 -p9 tck(min) 2.5 1.875 1.5 1.25 ns cas latency 658798109tck trcd(min) 15 12.5 15 13.125 13.5 12 12.5 11.25 ns trp(min) 15 12.5 15 13.125 13.5 12 12.5 11.25 ns tras(min) 37.5 37.5 37.5 37.5 36 36 35 35 ns trc(min) 52.5 50 52.5 50.625 49.5 48 47.25 46.25 ns cl-trcd-trp 6-6-6 5-5-5 8-8-8 7-7-7 9-9-9 8-8-8 10-10-10 9-9-9 tck 512mb 1gb 1gb 2gb 2gb organization 64m x 64 128m x 64 128m x 72 256m x 64 256m x 72 refresh method 8k/64ms 8k/64ms 8k/64ms 8k/64ms 8k/64ms row address a0-a12 a0-a13 a0-a13 a0-a13 a0-a13 column address a0-a9 a0-a9 a0-a9 a0-a9 a0-a9 bank address ba0-ba2 ba0-ba2 ba0-ba2 ba0-ba2 ba0-ba2 page size 2kb 1kb 1kb 1kb 1kb # of rank 11122 # of device 4 8 9 16 18
rev. 0.1 / dec 2008 7 hmt164u6afp(r)6c hmt112u6(7)afp(r)8c hmt125u6(7)afp(r)8c 2. pin architecture 2.1 pin definition pin name description pin name description a0?a13 sdram address bus scl i 2 c serial bus clock for eeprom ba0?ba2 sdram bank select sda i 2 c serial bus data line for eeprom ras sdram row address strobe sa0?sa2 i 2 c slave address select for eeprom cas sdram column address strobe v dd * sdram core power supply we sdram write enable v dd q * sdram i/o driver power supply s 0?s 1 dimm rank select lines v ref dq sdram i/o reference supply cke0?cke1 sdram clock enable lines v ref ca sdram command/address reference supply odt0?odt1 on-die termination control lines v ss power supply return (ground) dq0?dq63 dimm memory data bus v ddspd serial eeprom positive power supply cb0?cb7 dimm ecc check bits nc spare pins (no connect) dqs0?dqs8 sdram data strobes (positive line of differential pair) test memory bus analysis tools (unused on memory dimms) dqs 0?dqs 8 sdram data strobes (negative line of differential pair) reset set drams to known state dm0?dm8 sdram data masks/high data strobes (x8-based x72 dimms) v tt sdram i/o termination supply ck0?ck1 sdram clocks (positive line of differential pair) rfu reserved for future use ck 0?ck 1 sdram clocks (negative line of differential pair) - - *the v dd and v dd q pins are tied common to a sing le power-plane on these designs
rev. 0.1 / dec 2008 8 hmt164u6afp(r)6c hmt112u6(7)afp(r)8c hmt125u6(7)afp(r)8c 2.2 input/output functional description symbol type polarity function ck0?ck1 ck 0?ck 1 sstl differential crossing ck and ck are differential clock inputs. all the ddr3 sdram addr/cntl inputs are sampled on the crossing of positive edge of ck and negative edge of ck . output (read) data is referenc e to the crossing of ck and ck (both directions of crossing). cke0?cke1 sstl active high activates the sdram ck si gnal when high and deac tivates the ck signal when low. by deactivating the cloc ks, cke low initiates the power down mode, or the self refresh mode. s 0?s 1sstlactive low enables the associated sdram command decoder when low and disables the command decoder when high. wh en the command decoder is dis- abled, new commands are ignored but previous operations continue. this signal provides for external rank selection on systems with multiple ranks. ras , cas, we sstl active low ras , cas , and we ( along with s ) define the command being entered. odt0?odt1 sstl active high when high, termination resistance is enabled for all dq, dqs, dqs and dm pins, assuming this function is enabled in the mode register 1 (mr1). v ref dq supply reference voltage for sstl15 i/o inputs. v ref ca supply reference voltage for sstl 15 command/address inputs. v dd q supply power supply for the ddr3 sdram output buffers to provide improved noise immunity. for all current ddr3 unbuffered dimm designs, v dd q shares the same power plane as v dd pins. ba0?ba2 sstl ? selects which sdram bank of eight is activated. a0?a13 sstl ? during a bank activate command cycle, address input defines the row address (ra0?ra15). during a read or write command cycl e, address input defines the column address. in addition to the column a ddress, ap is used to invoke autopre- charge operation at the end of the burst read or write cycle. if ap is high, autoprecharge is selected and ba0, ba1, ba2 defines the bank to be pre- charged. if ap is low, autoprecharge is disabled. during a precharge com- mand cycle, ap is used in conjunction with ba0, ba1, ba2 to control which bank(s) to precharge. if ap is high, all banks will be precharged regardless of the state of ba0, ba1 or ba2. if ap is low, ba0, ba1 and ba2 are used to define which bank to precharge. a12(bc ) is sampled during read and write commands to determine if burs t chop (on-the-fly) will be per- formed (high, no burst ch op; low, burst chopped). dq0?dq63, cb0?cb7 sstl ? data and check bit input/output pins. dm0?dm8 sstl active high dm is an input mask signal for write data. input data is masked when dm is sampled high coincident with that input data during a write access. dm is sampled on both edges of dqs. alth ough dm pins are input only, the dm loading matches the dq and dqs loading. v dd , v ss supply power and ground for the ddr3 sdram input buffers, and core logic. v dd and v dd q pins are tied to v dd /v dd q planes on these modules.
rev. 0.1 / dec 2008 9 hmt164u6afp(r)6c hmt112u6(7)afp(r)8c hmt125u6(7)afp(r)8c 2.3 pin assignment dqs0?dqs8 dqs 0?dqs 8 sstl differential crossing data strobe for input and output data. sa0?sa2 ? these signals are tied at the system planar to either v ss or v ddspd to con- figure the serial spd eeprom address range. sda ? this bidirectional pin is used to tr ansfer data into or out of the spd eeprom. an external resistor may be connected from the sda bus line to v ddspd to act as a pullup on the system board. scl ? this signal is used to clock data into and out of th e spd eeprom. an external resistor may be connec ted from the scl bus time to v ddspd to act as a pullup on the system board. v ddspd supply power supply for spd eeprom. this supply is separate from the v dd /v dd q power plane. eeprom supply is operable from 3.0v to 3.6v. front side(left 1?60) back side(right 121?180) front side(left 61?120) back side(right 181?240) pin # x64 non-ecc x72 ecc pin # x64 non-ecc x72 ecc pin # x64 non-ecc x72 ecc pin # x64 non-ecc x72 ecc 1v ref dq v ref dq 121 v ss v ss 61 a2 a2 181 a1 a1 2v ss v ss 122 dq4 dq4 62 v dd v dd 182 v dd v dd 3 dq0 dq0 123 dq5 dq5 63 ck1 ck1 183 v dd v dd 4dq1 dq1124 v ss v ss 64 ck 1ck 1184 ck0 ck0 5 v ss v ss 125 dm0 dm0 65 v dd v dd 185 ck 0ck 0 6dqs 0dqs 0 126 nc nc 66 v dd v dd 186 v dd v dd 7 dqs0 dqs0 127 v ss v ss 67 v ref ca v ref ca 187 nc nc 8 v ss v ss 128 dq6 dq6 68 nc nc 188 a0 a0 9 dq2 dq2 129 dq7 dq7 69 v dd v dd 189 v dd v dd 10 dq3 dq3 130 v ss v ss 70 a10 a10 190 ba1 2 ba1 2 11 v ss v ss 131 dq12 dq12 71 ba0 2 ba0 2 191 v dd v dd 12 dq8 dq8 132 dq13 dq13 72 v dd v dd 192 ras ras 13 dq9 dq9 133 v ss v ss 73 we we 193 s 0s 0 14 v ss v ss 134 dm1 dm1 74 cas cas 194 v dd v dd 15 dqs 1dqs 1 135 nc nc 75 v dd v dd 195 odt0 odt0 16 dqs1 dqs1 136 v ss v ss 76 s1 s1 196 a13 a13 nc = no connect; rfu = reserved future use 1. nc pins should not be connected to anything on the dimm, including bussi ng within the nc group. 2. address pins a3?a8 and ba0 and ba1 can be mirrored or not mirrored. please refer to section 4.1 for more information on mirrored addresses. symbol type polarity function
rev. 0.1 / dec 2008 10 hmt164u6afp(r)6c hmt112u6(7)afp(r)8c hmt125u6(7)afp(r)8c 17 v ss v ss 137 dq14 dq14 77 odt1 odt1 197 v dd v dd 18 dq10 dq10 138 dq15 dq15 78 v dd v dd 198 nc nc 19 dq11 dq11 139 v ss v ss 79 nc nc 199 v ss v ss 20 v ss v ss 140 dq20 dq20 80 v ss v ss 200 dq36 dq36 21 dq16 dq16 141 dq21 dq21 81 dq32 dq32 201 dq37 dq37 22 dq17 dq17 142 v ss v ss 82 dq33 dq33 202 v ss v ss 23 v ss v ss 143 dm2 dm2 83 v ss v ss 203 dm4 dm4 24 dqs 2dqs 2144 nc nc 84 dqs 4dqs 4 204 nc nc 25 dqs2 dqs2 145 v ss v ss 85 dqs4 dqs4 205 v ss v ss 26 v ss v ss 146 dq22 dq22 86 v ss v ss 206 dq38 dq38 27 dq18 dq18 147 dq23 dq23 87 dq34 dq34 207 dq39 dq39 28 dq19 dq19 148 v ss v ss 88 dq35 dq35 208 v ss v ss 29 v ss v ss 149 dq28 dq28 89 v ss v ss 209 dq44 dq44 30 dq24 dq24 150 dq29 dq29 90 dq40 dq40 210 dq45 dq45 31 dq25 dq25 151 v ss v ss 91 dq41 dq41 211 v ss v ss 32 v ss v ss 152 dm3 dm3 92 v ss v ss 212 dm5 dm5 33 dqs 3dqs 3 153 nc nc 93 dqs 5dqs 5 213 nc nc 34 dqs3 dqs3 154 v ss v ss 94 dqs5 dqs5 214 v ss v ss 35 v ss v ss 155 dq30 dq30 95 v ss v ss 215 dq46 dq46 36 dq26 dq26 156 dq31 dq31 96 dq42 dq42 216 dq47 dq47 37 dq27 dq27 157 v ss v ss 97 dq43 dq43 217 v ss v ss 38 v ss v ss 158 nc cb4 98 v ss v ss 218 dq52 dq52 39 nc cb0 159 nc cb5 99 dq48 dq48 219 dq53 dq53 40 nc cb1 160 v ss v ss 100 dq49 dq49 220 v ss v ss 41 v ss v ss 161 dm8 dm8 101 v ss v ss 221 dm6 dm6 42 nc dqs 8 162 nc nc 102 dqs 6dqs 6 222 nc nc 43 nc dqs8 163 v ss v ss 103 dqs6 dqs6 223 v ss v ss 44 v ss v ss 164 nc cb6 104 v ss v ss 224 dq54 dq54 45 nc cb2 165 nc cb7 105 dq50 dq50 225 dq55 dq55 46 nc cb3 166 v ss v ss 106 dq51 dq51 226 v ss v ss 47 v ss v ss 167 nc nc 107 v ss v ss 227 dq60 dq60 front side(left 1?60) back side(right 121?180) front side(left 61?120) back side(right 181?240) pin # x64 non-ecc x72 ecc pin # x64 non-ecc x72 ecc pin # x64 non-ecc x72 ecc pin # x64 non-ecc x72 ecc nc = no connect; rfu = reserved future use 1. nc pins should not be connected to anything on the dimm, including bussi ng within the nc group. 2. address pins a3?a8 and ba0 and ba1 can be mirrored or not mirrored. please refer to section 4.1 for more information on mirrored addresses.
rev. 0.1 / dec 2008 11 hmt164u6afp(r)6c hmt112u6(7)afp(r)8c hmt125u6(7)afp(r)8c 48 nc nc 168 reset reset 108 dq56 dq56 228 dq61 dq61 key key 109 dq57 dq57 229 v ss v ss 49 nc nc 169 cke1/nc cke1/nc 110 v ss v ss 230 dm7 dm7 50 cke0 cke0 170 v dd v dd 111 dqs 7dqs 7 231 nc nc 51 v dd v dd 171 nc nc 112 dqs7 dqs7 232 v ss v ss 52 ba2 ba2 172 nc nc 113 v ss v ss 233 dq62 dq62 53 nc nc 173 v dd v dd 114 dq58 dq58 234 dq63 dq63 54 v dd v dd 174 a12 a12 115 dq59 dq59 235 v ss v ss 55 all all 175 a9 a9 116 v ss v ss 236 v ddspd v ddspd 56 a7 2 a7 2 176 v dd v dd 117 sa0 sa0 237 sa1 sa1 57 v dd v dd 177 a8 2 a8 2 118 scl scl 238 sda sda 58 a5 2 a5 2 178 a6 2 a6 2 119 sa2 sa2 239 v ss v ss 59 a4 2 a4 2 179 v dd v dd 120 v tt v tt 240 v tt v tt 60 v dd v dd 180 a3 2 a3 2 front side(left 1?60) back side(right 121?180) front side(left 61?120) back side(right 181?240) pin # x64 non-ecc x72 ecc pin # x64 non-ecc x72 ecc pin # x64 non-ecc x72 ecc pin # x64 non-ecc x72 ecc nc = no connect; rfu = reserved future use 1. nc pins should not be connected to anything on the dimm, including bussi ng within the nc group. 2. address pins a3?a8 and ba0 and ba1 can be mirrored or not mirrored. please refer to section 4.1 for more information on mirrored addresses.
rev. 0.1 / dec 2008 12 hmt164u6afp(r)6c hmt112u6(7)afp(r)8c hmt125u6(7)afp(r)8c 3. functional block diagram 3.1 512mb, 64mx64 mo dule(1rank of x16) dq4 dq5 dq6 dq7 dq0 dq1 dq2 dq3 i/o 0 i/o 1 i/o 2 i/o 3 d0 dm0 i/o 4 i/o 5 i/o 6 i/o 7 dq12 dq13 dq14 dq8 dq9 dq10 dq11 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 dm1 a0?a14 a0?a14: sdrams d0?d3 a0 serial pd a1 sa0 sa1 sda ras ras : sdrams d0?d3 cas cas : sdrams d0?d3 cke0 cke: sdrams d0?d3 we we : sdrams d0?d3 cs cs cs ba0?ba2 ba0?ba2: sdrams d0?d3 dqs0 dqs1 dq15 i/o 15 v ss d0?d3 v dd /v dd q d0?d3 d0?d3 v ref dq notes: 1. dq-to-i/o wiring is shown as recom- mended but may be changed. 2. dq/dqs/dqs /odt/dm/cke/s relation- ships must be maintained as shown. 3. dq,dm,dqs,dqs resistors;refer to asso- ciated topology diagram. 4. refer to the approp riate clock wiring topology under the dimm wiring details section of this document. 5. the pair ck1 and ck1# is terminated in 75ohm but is not used on the module. 6. a15 is not routed on the module. 7. for each dram, a unique zq resistor is connected to ground.the zq resistor is 240ohm+-1% 8. one spd exists per module. scl wp spd v ddspd odt0 dqs 0 dqs 1 odt: sdrams d0?d3 s 0 ck0 ck: sdrams d0?d3 sa2 d0?d3 v ref ca a2 ck 0ck : sdrams d0?d3 ldqs ldqs ldm udqs udqs udm dq20 dq21 dq22 dq23 dq16 dq17 dq18 dq19 i/o 0 i/o 1 i/o 2 i/o 3 d1 dm2 i/o 4 i/o 5 i/o 6 i/o 7 dq28 dq29 dq30 dq24 dq25 dq26 dq27 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 dm3 cs dqs2 dqs3 dq31 i/o 15 dqs2 dqs3 ldqs ldqs ldm udqs udqs udm dq36 dq37 dq38 dq39 dq32 dq33 dq34 dq35 i/o 0 i/o 1 i/o 2 i/o 3 d2 dm4 i/o 4 i/o 5 i/o 6 i/o 7 dq44 dq45 dq46 dq40 dq41 dq42 dq43 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 dm5 cs cs cs dqs4 dqs5 dq47 i/o 15 dqs 4 dqs5 ldqs ldqs ldm udqs udqs udm dq52 dq53 dq54 dq55 dq48 dq49 dq50 dq51 i/o 0 i/o 1 i/o 2 i/o 3 d3 dm6 i/o 4 i/o 5 i/o 6 i/o 7 dq60 dq61 dq62 dq56 dq57 dq58 dq59 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 dm7 cs dqs6 dqs7 dq63 i/o 15 dqs6 dqs7 ldqs ldqs ldm udqs udqs udm reset reset :sdrams d0-d3 zq zq zq zq
rev. 0.1 / dec 2008 13 hmt164u6afp(r)6c hmt112u6(7)afp(r)8c hmt125u6(7)afp(r)8c 3.2 1gb, 128m x64 module(1rank of x8) dq4 dq5 dq6 dq7 dq0 dq1 dq2 dq3 dm i/o 0 i/o 1 i/o 2 i/o 3 d0 dm0 i/o 4 i/o 5 i/o 6 i/o 7 dq12 dq13 dq14 dq8 dq9 dq10 dq11 dm i/o 0 i/o 1 i/o 2 i/o 3 d1 i/o 4 i/o 5 i/o 6 dm1 dq20 dq21 dq22 dq23 dq16 dq17 dq18 dq19 dm i/o 0 i/o 1 i/o 2 i/o 3 d2 i/o 4 i/o 5 i/o 6 i/o 7 dm2 dq28 dq29 dq30 dq31 dq24 dq25 dq26 dq27 dm i/o 0 i/o 1 i/o 2 i/o 3 d3 i/o 4 i/o 5 i/o 6 i/o 7 dm3 dq36 dq37 dq38 dq39 dq32 dq33 dq34 dq35 dm i/o 0 i/o 1 i/o 2 i/o 3 d4 dm4 i/o 4 i/o 5 i/o 6 i/o 7 dq44 dq45 dq46 dq47 dq40 dq41 dq42 dq43 dm i/o 0 i/o 1 i/o 2 i/o 3 d5 i/o 4 i/o 5 i/o 6 i/o 7 dm5 dq52 dq53 dq54 dq55 dq48 dq49 dq50 dq51 dm i/o 0 i/o 1 i/o 2 i/o 3 d6 i/o 4 i/o 5 i/o 6 i/o 7 dq60 dq61 dq62 dq63 dq56 dq57 dq58 dq59 dm i/o 0 i/o 1 i/o 2 i/o 3 d7 i/o 4 i/o 5 i/o 6 i/o 7 dm7 a0?a15 a0?a15: sdrams d0?d7 a0 serial pd a1 sa0 sa1 sda ras ras : sdrams d0?d7 cas cas : sdrams d0?d7 cke0 cke: sdrams d0?d7 we we : sdrams d0?d7 cs cs cs cs cs cs cs cs ba0?ba2 ba0?ba2: sdrams d0?d7 dqs0 dqs dqs4 dqs1 dqs5 dqs dqs 2 dqs dqs3 dqs dm6 dqs6 dqs7 dq15 i/o 7 dqs dqs dqs dqs v ss d0?d7 v dd /v dd q d0?d7 d0?d7 v ref dq scl wp spd v ddspd odt0 dqs 0 dqs dqs dqs 4 dqs 1 dqs dqs dqs2 dqs dqs 3 dqs dqs 5 dqs 6 dqs dqs 7 dqs odt: sdrams d0?d7 s 0 ck0 ck: sdrams d0?d7 sa2 d0?d7 v ref ca a2 ck 0ck : sdrams d0?d7 zq zq zq zq zq zq zq zq reset reset :sdrams d0-d7 notes: 1. dq-to-i/o wiring is shown as recom- mended but may be changed. 2. dq/dqs/dqs /odt/dm/cke/s relation- ships must be maintained as shown. 3. dq,dm,dqs/dqs resistors;refer to associated topology diagram. 4. refer to the approp riate clock wiring topology under the dimm wiring details section of this document. 5. refer to section 3.1 of this document for details on address mirroring. 6. for each dram, a unique zq resistor is connected to ground.the zq resistor is 240ohm+-1% 7. one spd exists per module.
rev. 0.1 / dec 2008 14 hmt164u6afp(r)6c hmt112u6(7)afp(r)8c hmt125u6(7)afp(r)8c 3.3 1gb, 128m x72 module(1rank of x8) dq4 dq5 dq6 dq7 dq0 dq1 dq2 dq3 dm i/o 0 i/o 1 i/o 2 i/o 3 d0 dm0 i/o 4 i/o 5 i/o 6 i/o 7 dq12 dq13 dq14 dq8 dq9 dq10 dq11 dm i/o 0 i/o 1 i/o 2 i/o 3 d1 i/o 4 i/o 5 i/o 6 dm1 dq20 dq21 dq22 dq23 dq16 dq17 dq18 dq19 dm i/o 0 i/o 1 i/o 2 i/o 3 d2 i/o 4 i/o 5 i/o 6 i/o 7 dm2 dq28 dq29 dq30 dq31 dq24 dq25 dq26 dq27 dm i/o 0 i/o 1 i/o 2 i/o 3 d3 i/o 4 i/o 5 i/o 6 i/o 7 dm3 dq36 dq37 dq38 dq39 dq32 dq33 dq34 dq35 dm i/o 0 i/o 1 i/o 2 i/o 3 d4 dm4 i/o 4 i/o 5 i/o 6 i/o 7 dq44 dq45 dq46 dq47 dq40 dq41 dq42 dq43 dm i/o 0 i/o 1 i/o 2 i/o 3 d5 i/o 4 i/o 5 i/o 6 i/o 7 dm5 dq52 dq53 dq54 dq55 dq48 dq49 dq50 dq51 dm i/o 0 i/o 1 i/o 2 i/o 3 d6 i/o 4 i/o 5 i/o 6 i/o 7 dq60 dq61 dq62 dq63 dq56 dq57 dq58 dq59 dm i/o 0 i/o 1 i/o 2 i/o 3 d7 i/o 4 i/o 5 i/o 6 i/o 7 dm7 a0?a15 a0?a15: sdrams d0?d8 a0 spd(ts integrated) a1 sa0 sa1 sda ras ras : sdrams d0?d8 cas cas : sdrams d0?d8 cke0 cke: sdrams d0?d8 we we : sdrams d0?d8 s 0 cs cs cs cs cs cs cs cs ba0?ba2 ba0?ba2: sdrams d0?d8 dqs0 dqs dqs4 dqs1 dqs5 dqs dqs 2 dqs dqs3 dqs dm6 dqs6 dqs7 dq15 i/o 7 cb4 cb5 cb6 cb7 cb0 cb1 cb2 cb3 dm i/o 0 i/o 1 i/o 2 i/o 3 d8 i/o 4 i/o 5 i/o 6 i/o 7 cs dqs8 dm8 dqs dqs dqs dqs dqs v ss d0?d8 v dd /v dd q d0?d8 d0?d8 v ref dq scl event spd v ddspd odt0 odt: sdrams d0?d8 dqs 0 dqs dqs dqs 4 dqs 1 dqs dqs dqs2 dqs dqs 3 dqs dqs 8 dqs dqs 5 dqs 6 dqs dqs 7 dqs ck0 ck: sdrams d0?d8 sa2 v ref ca d0?d8 a2 ck 0ck : sdrams d0?d8 zq zq zq zq zq zq zq zq zq reset reset :sdrams d0-d8 notes: 1. dq-to-i/o wiring is shown as recom- mended but may be changed. 2. dq/dqs/dqs /odt/dm/cke/s rela- tionships must be maintained as shown. 3. dq,cb,dm,dqs/dqs resistors;refer to associated topology diagram. 4. refer to the appropriate clock wiring topology under the dimm wiring details section of this document. 5. for each dram, a unique zq resistor is connected to ground.the zq resis- tor is 240ohm+-1% 6. one spd exists per module. event
rev. 0.1 / dec 2008 15 hmt164u6afp(r)6c hmt112u6(7)afp(r)8c hmt125u6(7)afp(r)8c 3.4 2gb, 256mx64 module(2rank of x8) dq4 dq5 dq6 dq7 dq0 dq1 dq2 dq3 dm i/o 0 i/o 1 i/o 2 i/o 3 d0 dm0 d8 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dq12 dq13 dq14 dq8 dq9 dq10 dq11 i/o 0 i/o 1 i/o 2 i/o 3 d1 d9 i/o 4 i/o 5 i/o 6 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 dm1 dq20 dq21 dq22 dq23 dq16 dq17 dq18 dq19 i/o 0 i/o 1 i/o 2 i/o 3 d2 d10 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dm2 dq28 dq29 dq30 dq31 dq24 dq25 dq26 dq27 i/o 0 i/o 1 i/o 2 i/o 3 d3 d11 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dm3 dq36 dq37 dq38 dq39 dq32 dq33 dq34 dq35 i/o 0 i/o 1 i/o 2 i/o 3 d4 dm4 d12 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dq44 dq45 dq46 dq47 dq40 dq41 dq42 dq43 i/o 0 i/o 1 i/o 2 i/o 3 d5 d13 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dm5 dq52 dq53 dq54 dq55 dq48 dq49 dq50 dq51 i/o 0 i/o 1 i/o 2 i/o 3 d6 d14 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dq60 dq61 dq62 dq63 dq56 dq57 dq58 dq59 i/o 0 i/o 1 i/o 2 i/o 3 d7 d15 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dm7 a0?a15 a0-a15: sdrams d0?d15 a0 serial pd a1 sa0 sa1 sda ras ras : sdrams d0?d15 cas cas : sdrams d0?d15 we we : sdrams d0?d15 s 0 s 1 cs cke1 cke: sdrams d8?d15 ba0?ba2 ba0?ba2: sdrams d0?d15 dqs0 dqs dqs4 dqs1 dqs5 dqs2 dqs3 dm6 dqs6 dqs7 dq15 i/o 7 i/o 7 v ss d0?d15 v dd /v dd q d0?d15 d0?d15 v ref dq scl wp spd v ddspd dqs dm cs dqs dqs dm cs dqs dqs dm cs dqs dqs dm cs dqs dqs dm cs dqs dqs dm cs dqs dqs dm cs dqs dqs dm cs dqs dqs dm cs dqs dqs dm cs dqs dqs dm cs dqs dqs dm cs dqs dqs dm cs dqs dqs dm cs dqs dqs dm cs dqs dqs dqs 0 dqs 4 dqs 1 dqs 5 dqs 2 dqs 6 dqs 3 dqs 7 odt0 odt: sdrams d0?d7 odt1 odt: sdrams d8?d15 cke0 cke: sdrams d0?d7 ck0 ck: sdrams d0?d7 ck 0ck : sdrams d0?d7 sa2 d0?d15 v ref ca a2 ck1 ck: sdrams d8?d15 ck 1ck : sdrams d8?d15 zq zq zq zq zq zq zq zq zq zq zq zq zq zq zq zq reset reset :sdrams d0-d3 notes: 1. dq-to-i/o wiring is shown as recom- mended but may be changed. 2. dq/dqs/dqs /odt/dm/cke/s relation- ships must be maintained as shown. 3. dq,dm,dqs,dqs resistors;refer to associated topo logy diagram. 4. refer to section 3.1 of this document for details on address mirroring. 5. for each dram, a unique zq resistor is connected to ground.the zq resistor is 240ohm+-1% 6. one spd exists per module.
rev. 0.1 / dec 2008 16 hmt164u6afp(r)6c hmt112u6(7)afp(r)8c hmt125u6(7)afp(r)8c 3.5 2gb, 256mx72 mo dule(2rank of x8) dq4 dq5 dq6 dq7 dq0 dq1 dq2 dq3 i/o 1 i/o 2 i/o 3 d0 d9 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dq12 dq13 dq14 dq8 dq9 dq10 dq11 i/o 0 i/o 1 i/o 2 i/o 3 d1 d10 i/o 4 i/o 5 i/o 6 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 dq20 dq21 dq22 dq23 dq16 dq17 dq18 dq19 i/o 0 i/o 1 i/o 2 i/o 3 d2 d11 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dq28 dq29 dq30 dq31 dq24 dq25 dq26 dq27 i/o 0 i/o 1 i/o 2 i/o 3 d3 d12 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dq36 dq37 dq38 dq39 dq32 dq33 dq34 dq35 i/o 0 i/o 1 i/o 2 i/o 3 d4 d13 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dq44 dq45 dq46 dq47 dq40 dq41 dq42 dq43 i/o 0 i/o 1 i/o 2 i/o 3 d5 d14 i/o 4 i/o 5 i/o 6 i/o 7 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dq52 dq53 dq54 dq55 dq48 dq49 dq50 dq51 i/o 0 i/o 1 i/o 2 i/o 3 d6 d15 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dq60 dq61 dq62 dq63 dq56 dq57 dq58 dq59 i/o 0 i/o 1 i/o 2 i/o 3 d7 d16 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 a0?a15 a0-a15: sdrams d0?d17 ras ras : sdrams d0?d17 cas cas : sdrams d0?d17 we we : sdrams d0?d17 cke1 cke: sdrams d9?d17 ba0?ba2 ba0-ba2: sdrams d0?d17 dq15 i/o 7 i/o 7 cb4 cb5 cb6 cb7 cb0 cb1 cb2 cb3 i/o 0 i/o 1 i/o 2 i/o 3 d8 d17 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqs8 dm8 vss d0?d17 v dd /v dd q d0?d17 d0?d17 v ref dq spd v ddspd dm cs dqs dqs dm cs dqs dqs dm cs dqs dqs dm cs dqs dqs dm cs dqs dqs dm cs dqs dqs dm cs dqs dqs dm cs dqs dqs dm cs dqs dqs dm cs dqs dqs dm cs dqs dqs dm cs dqs dqs dm cs dqs dqs dm cs dqs dqs dm cs dqs dqs dm cs dqs dqs dm cs dqs dqs dm cs dqs dqs i/o 0 i/o 0 dm0 dm4 s 0 s 1 dqs0 dqs4 dqs 0 dqs 4 dm1 dm5 dqs1 dqs5 dqs 1dqs 5 dm2 dqs2 dm6 dqs6 dqs 2 dm3 dm7 dqs3 dqs7 dqs 3 dqs 7 dqs 6 dqs 8 odt0 odt: sdrams d0?d8 odt1 odt: sdrams d9?d17 cke0 cke: sdrams d0?d8 ck0 ck: sdrams d0?d8 ck 0ck : sdrams d0?d8 d0?d17 v ref ca ck1 ck: sdrams d9?d17 ck 1ck : sdrams d9?d17 zq zq zq zq zq zq zq zq zq zq zq zq zq zq zq zq zq zq reset reset :sdrams d0-d17 notes: 1. dq-to-i/o wiring is shown as recom- mended but may be changed. 2. dq/dqs/dqs /odt/dm/cke/s relation- ships must be maintained as shown. 3. dq,cb,dm/dqs/dqs resistors;refer to associated topology diagram. 4. refer to section 3.1 of this document for details on addr ess mirroring. 5. for each dram, a unique zq resistor is connected to ground.the zq resistor is 240ohm+-1% 6. one spd exists per module. a0 spd(ts integrated) a1 sa0 sa1 sda scl event sa2 a2 event
rev. 0.1 / dec 2008 17 hmt164u6afp(r)6c hmt112u6(7)afp(r)8c hmt125u6(7)afp(r)8c 4. address mirroring feature there is a via grid located under the sdrams for wiring th e ca signals (address, bank ad dress, command, and control lines) to the sdram pins. the length of the traces from the via to the sdrams places limitations on the bandwidth of the module. the shorter these traces, the higher the bandwi dth. to extend the bandwidt h of the ca bus for ddr3 modules, a scheme was defined to reduce the length of th ese traces.the pins on the sdram are defined in a manner that allows for these short trace length s. the ca bus pins in columns 2 and 8, ignoring the mechanical support pins, do not have any special functions (secondary functions). th is allows the most flexibility with these pins. these are address pins a3, a4, a5, a6, a7, a8 and bank address pins ba0 and ba1. refer to table . rank 0 sdram pins are wired straight, with no mismatch betw een the connector pin assignment and th e sdram pin assignment. some of the rank 1 sdram pins are cross wired as defined in the ta ble. pins not listed in the table are wired straight. 4.1 dram pin wiri ng for mirroring
the table 4.1 illustrates the wiring in both the mirrored and non-mirrored case. the lengths of the traces to the sdram pins, is ob viously shorter. the via grid is smaller as well. connector pin sdram pin rank 0 rank 1 a3 a3 a4 a4 a4 a3 a5 a5 a6 a6 a6 a5 a7 a7 a8 a8 a8 a7 ba0 ba0 ba1 ba1 ba1 ba0
rev. 0.1 / dec 2008 18 hmt164u6afp(r)6c hmt112u6(7)afp(r)8c hmt125u6(7)afp(r)8c < figure 4.1: wiring differences for mirrored and non-mirrored addresses > since the cross-wired pins have no secondary functions, ther e is no problem in normal operation. any data written is read the same way. there are limitation s however. when writing to the intern al registers with a "load mode" opera- tion, the specific address is requ ired. this requires the controll er to know if the rank is mi rrored or not. this requires a few rules. mirroring is done on 2 rank modules and can only be done on the second rank. there is not a requirement that the second rank be mirrored. there is a bit assignme nt in the spd that indicates whether the module has been designed with the mirrored feature or not. see the ddr3 ud imm spd specification for thes e details. the controller must read the spd and have the capability of de-mir roring the address when accessing the second rank. no mirroring mirroring
rev. 0.1 / dec 2008 19 hmt164u6afp(r)6c hmt112u6(7)afp(r)8c hmt125u6(7)afp(r)8c 5. absolute maximum ratings 5.1 absolute maxi mum dc ratings 5.2 dram component ope rating temperature range symbol parameter rating units notes vdd voltage on vdd pin relative to vss - 0.4 v ~ 1.975 v v ,3 vddq voltage on vddq pin relative to vss - 0.4 v ~ 1.975 v v ,3 vin, vout voltage on any pin relative to vss - 0.4 v ~ 1.975 v v tstg storage temperature -55 to +100 ? ? , 2 1. stresses greater than those listed under ?absolut e maximum ratings? may cause permanent damage to the device. this is a stress rating only and function al operation of the device at these or any other conditions above those indicated in the oper ational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. storage temperature is the case surface temperature on the center/top side of the dram. for the measurement conditions, please refer to jesd51-2 standard. 3. vdd and vddq must be within 300mv of each othe r at all times;and vref must be not greater than 0.6xvddq,when vdd and vddq are less than 500mv; vref may be equal to or less than 300mv. symbol parameter rating units notes toper normal temperature range 0 to 85 ? ,2 extended temperature range 85 to 95 ? 1,3 1. operating temperature toper is the case surface temperature on the center / top side of the dram. for measurement conditions, please refer to the jedec document jesd51-2. 2. the normal temperature range specifies the temperat ures where all dram specifications will be supported. during operation, the dram case temperature must be maintained between 0 - 85oc under all operating conditions 3. some applications require operation of the dram in the extended temperature range between 85? and 95? case temperature. full specifications are guaranteed in this range, but the following additional conditions apply: a) refresh commands must be doubled in frequency, therefore reducing the refresh interval trefi to 3.9 s. (this double refresh requirement may not apply for some devices.) it is also possible to specify a component with 1x refresh (trefi to 7.8s) in the extend ed temperature range. please refer to supplier data sheet and/ or the dimm spd for option avail ability. b) if self-refresh operation is required in the extend ed temperature range, than it is mandatory to either use the manual self-refresh mode with extended temperature range capability (mr2 a6 = 0band mr2 a7 = 1b) or enable the optional auto self-refresh mode (mr2 a6 = 1b and mr2 a7 = 0b).
rev. 0.1 / dec 2008 20 hmt164u6afp(r)6c hmt112u6(7)afp(r)8c hmt125u6(7)afp(r)8c 6. ac & dc operating conditions 6.1 recommended dc operating conditions 6.2 dc & ac logic input levels 6.2.1 dc & ac logic input levels for single-ended signals the dc-tolerance limits and ac-noise limits for the referenc e voltages vrefca and vrefdq are illustrated in figure 6.2.1. it shows a valid reference voltage vref(t) as a func tion of time. (vref stands for vrefca and vrefdq like- wise).vref(dc) is the linear average of vref(t) over a very long period of time (e.g. 1 sec). this average has to meet the min/max requirements in table 1. furthermore vref(t) may temporarily deviate from vref(dc) by no more than +/- 1% vdd. symbol parameter rating units notes min. typ. max. vdd supply voltage 1.425 1.500 1.575 v 1,2 vddq supply voltage for output 1.425 1.500 1.575 v 1,2 1. under all conditions, vddq must be less than or equal to vdd. 2. vddq tracks with vdd. ac parameters are measured with vdd abd vddq tied together. symbol parameter ddr3-800, ddr3-1066, ddr3-1333, ddr3-1600 unit notes min max vih(dc) dc input logic high vref + 0.100 - v 1, 2 vil(dc) dc input logic low vref - 0.100 v 1, 2 vih(ac) ac input logic high vref + 0.175 - v 1, 2 vil(ac) ac input logic low vref - 0.175 v 1, 2 vrefdq(dc) reference voltage for dq, dm inputs 0.49 * vdd 0.51 * vdd v 3, 4 vrefca(dc) reference voltage for add, cmd inputs 0.49 * vdd 0.51 * vdd v 3, 4 vtt termination voltage for dq, dqs outputs vddq/2 - tbd vddq/2 + tbd v 1. for dq and dm, vref = vrefdq. for inpu t ony pins except reset#, vref = vrefca. 2. the ?t.b.d.? entries might change based on overshoot and undershoot specification. 3. the ac peak noise on vref may not allow vref to deviate from vref(dc) by more than +/-1% vdd (for reference: approx. +/- 15 mv). for reference: approx. vdd/2 +/- 15 mv.
rev. 0.1 / dec 2008 21 hmt164u6afp(r)6c hmt112u6(7)afp(r)8c hmt125u6(7)afp(r)8c < figure 6.2.1: illustration of vref(dc) tolerance an d vref ac-noise limits > the voltage levels for setup and hold time measurements vih(ac), vih(dc), vil(ac) and vil(dc) are dependent on vref. "vref " shall be understood as vref(dc), as defined in figure 6.2.1 this clarifies, that dc-variations of vref affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to which setup and hold is me asured. system timing and voltage budgets need to account for vref(dc) deviations from the optimum positi on within the data-eye of the input signals. this also clarifies that the dram setup/ hold specification and derating values ne ed to include time and voltage associ- ated with vref ac-noise. timing and volt age effects due to ac-noise on vref up to the specified limit (+/-1% of vdd) are included in dram timings and their associated deratings. 6.2.2 dc & ac logic input leve ls for differential signals note1: refer to ?overshoot and undershoot specification section 6.5 on 26 page symbol parameter ddr3-800, ddr3-1066, ddr3-1333, ddr3-1600 unit notes min max vihdiff differential input logic high + 0.200 - v 1 vildiff differential input logic low - 0.200 v 1 vdd vss vdd/2 v ref(dc) v ref ac-noise voltage time v ref(dc)max v ref(dc)min v ref (t)
rev. 0.1 / dec 2008 22 hmt164u6afp(r)6c hmt112u6(7)afp(r)8c hmt125u6(7)afp(r)8c 6.2.3 differential inpu t cross point voltage to guarantee tight setup and hold times as well as output skew parameters wi th respect to clock and strobe, each cross point voltage of differential inpu t signals (ck, ck# and dqs, dqs#) must meet the requirements in table 6.2.3 the differential input cross point voltage vix is measured from the actual cross point of tr ue and complement signal to the midlevel between of vdd and vss. < figure 6.2.3 vix definition > < table 6.2.3: cross point voltage for di fferential input signals (ck, dqs) > symbol parameter ddr3-800, ddr3-1066, ddr3-1333, ddr3-1600 unit notes min max v ix differential input cross point voltage relative to vdd/2 - 150 + 150 mv vdd vss vdd/2 v ix v ix v ix ck#, dqs# ck, dqs
rev. 0.1 / dec 2008 23 hmt164u6afp(r)6c hmt112u6(7)afp(r)8c hmt125u6(7)afp(r)8c 6.3 slew rate definitions 6.3.1 for single ended input signals - input slew rate for input setup time (tis) and data setup time (tds) setup (tis and tds) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of vref and the first crossing of vih(ac)min. setup (tis and tds) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of vref and the first crossing of vil(ac)max. - input slew rate for input hold ti me (tih) and data hold time (tdh) hold nominal slew rate for a rising signal is defined as the slew rate between the last crossing of vil(dc)max and the first crossing of vref. hold (tih and tdh) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of vih( dc)min and the first crossing of vref. < table 6.3.1: single-ended input slew rate definition > description measured defined by applicable for min max input slew rate for rising edge vref vih(ac)min vih(ac)min-vref delta trs setup (tis, tds) input slew rate for falling edge vref vil(ac)max vref-vil(ac)max delta tfs input slew rate for rising edge vil(dc)max vref vref-vil(dc)max delta tfh hold (tih, tdh) input slew rate for falling edge vih(dc)min vref vih(dc)min-vref delta trh delta tfs delta trs vih(ac)min vih(dc)min vil(dc)max vil(ac)max vrefdq or vrefca part a: set up single ended input voltage(dq,add, cmd)
rev. 0.1 / dec 2008 24 hmt164u6afp(r)6c hmt112u6(7)afp(r)8c hmt125u6(7)afp(r)8c < figure 6.3.1: input nominal slew rate definition for single-ended signals > 6.3.2 differential input signals input slew rate for differential signals (ck, ck# and dqs, dqs#) are defined and measured as shown in below table and figure . note: the differential signal (i.e. ck-ck and dqs-dq s) must be linear between these thresholds. description measured defined by min max differential input slew rate for rising edge (ck-ck and dqs-dqs) vildiffmax vihdiffmin vihdiffmin-vildiffmax deltatrdiff differential input slew rate for falling edge (ck-ck and dqs-dqs) vihdiffmin vildiffmax vihdiffmin-vildiffmax deltatfdiff part b: hold delta tfh delta trh vih(ac)min vih(dc)min vil(dc)max vil(ac)max vrefdq or vrefca single ended input voltage(dq,add, cmd)
rev. 0.1 / dec 2008 25 hmt164u6afp(r)6c hmt112u6(7)afp(r)8c hmt125u6(7)afp(r)8c < figure 6.3.2: differential input slew ra te definition for dqs,dqs# and ck,ck# > 6.4 dc & ac output buffer levels 6.4.1 single ended dc & ac output levels below table shows the output levels used for measurements of single ended signals. symbol parameter ddr3-800, 1066, 1333 and 1600 unit notes voh(dc) dc output high measurement level (for iv curve linearity) 0.8 x vddq v vom(dc) dc output mid measurement level (for iv curve linearity) 0.5 x vddq v vol(dc) dc output low measurement level (for iv curve linearity) 0.2 x vddq v voh(ac) ac output high measurement level (for output sr) vtt + 0.1 x vddq v 1 vol(ac) ac output low measurement level (for output sr) vtt - 0.1 x vddq v 1 1. the swing of ? 1 x vddq is based on approximately 50% of the static single ended output high or low swing with a driver impedance of 40 ? and an effective test load of 25 ? to vtt = vddq / 2. delta tfdiff delta trdiff vihdiffm in vildiffm ax 0 differential input voltage (i.e. dqs-dqs; ck-ck)
rev. 0.1 / dec 2008 26 hmt164u6afp(r)6c hmt112u6(7)afp(r)8c hmt125u6(7)afp(r)8c 6.4.2 differential dc & ac output levels below table shows the output levels used for measurements of differential signals. 6.4.3 single ended output slew rate with the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between vol(ac) and voh(ac) for single ende d signals as shown in belo w table and figure 6.4.3. note: output slew rate is verified by design and characte rization, and may not be su bject to production test. < figure 6.4.3: single ended output slew rate definition > symbol parameter ddr3-800, 1066, 1333 and 1600 unit notes vohdiff (ac) ac differential output high measurement level (for output sr) + 0.2 x vddq v 1 voldiff (ac) ac differential output low measurement level (for output sr) - 0.2 x vddq v 1 1. the swing of ? 0.2 x vddq is based on appro ximately 50% of the static differential output high or low swingwith a driver impeda nce of 40?? and an effective test load of 25?? to vtt = vddq/2 at each of the differential output description measured defined by from to single ended output slew rate for rising edge vol(ac) voh(ac) voh(ac)-vol(ac) deltatrse single ended output slew rate for falling edge voh(ac) vol(ac) voh(ac)-vol(ac) deltatfse delta tfse delta trse voh(ac) vol(ac) v ? single ended output voltage(l.e.dq)
rev. 0.1 / dec 2008 27 hmt164u6afp(r)6c hmt112u6(7)afp(r)8c hmt125u6(7)afp(r)8c *** description: sr: slew rate q: query output (like in dq, which stands for data-in, query-output) for ron = rzq/7 setting < table 6.4.3: output slew rate (single-ended) > 6.4.4 differential output slew rate with the reference load for timing measurements, output sl ew rate for falling and rising edges is defined and mea- sured between voldiff(ac) and vohdiff(ac) for differentia l signals as shown in below table and figure 6.4.4 note: output slew rate is verified by design and charac terization, and may not be subject to production test. < figure 6.4.4: differential output slew rate definition > parameter symbol ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 units min max min max min max min max single-ended output slew rate srqse 2.5 5 2.5 5 2.5 5 tbd 5 v/ns description measured defined by from to differential output slew rate for rising edge voldiff(ac) vohdiff(ac) vohdiff(ac)-voldiff(ac) deltatrdiff differential output slew rate for falling edge vohdiff(ac) voldiff(ac) vohdiff(ac)-voldiff(ac) deltatfdiff delta tfdiff delta trdiff voldiff(ac) o differential output voltage(i.e. dqs-dqs) vohdiff(ac)
rev. 0.1 / dec 2008 28 hmt164u6afp(r)6c hmt112u6(7)afp(r)8c hmt125u6(7)afp(r)8c ***description: sr: slew rate q: query output (like in dq, which stands for data-in, query-output) diff: differential signals for ron = rzq/7 setting < table 6.6.4: differential output slew rate > 6.5 overshoot and undershoot specifications 6.5.1 address and control overshoot and undershoot specifications < table 6.5.1: ac overshoot/undershoot sp ecification for address and control pins > < figure 6.5.1: address and control overshoot and undershoot definition > parameter symbol ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 units min max min max min max min max differential output slew rate srqdiff 5 10 5 10 5 10 tbd 10 v/ns description specification ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 maximum peak amplitude allowed for overshoot area (see figure) 0.4v 0.4v 0.4v 0.4v maximum peak amplitude allowed for undershoot area (see figure) 0.4v 0.4v 0.4v 0.4v maximum overshoot area above vdd (see figure) 0.67 v-ns 0.5 v-ns 0.4 v-ns 0.33 v-ns maximum undershoot area below vss (see figure) 0.67 v-ns 0.5 v-ns 0.4 v-ns 0.33 v-ns maximum amplitude overshoot area vdd vss volts (v) maximum amplitude undershoot area time (ns)
rev. 0.1 / dec 2008 29 hmt164u6afp(r)6c hmt112u6(7)afp(r)8c hmt125u6(7)afp(r)8c 6.5.2 clock,data,strobe and mask overshoot and undershoot specifications < table 6.5.2: ac overshoot/undershoot specification for clock, data, strobe and mask > < figure 6.5.2: clock, data, strobe and mask overshoot and undershoot definition > description specification ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 maximum peak amplitude allowed for overshoot area (see figure) 0.4v 0.4v 0.4v 0.4v maximum peak amplitude allowed for undershoot area (see figure) 0.4v 0.4v 0.4v 0.4v maximum overshoot area above vddq (see figure) 0.25 v-ns 0.19 v-ns 0.15 v-ns 0.13 v-ns maximum undershoot area below vssq (see figure) 0.25 v-ns 0.19 v-ns 0.15 v-ns 0.13 v-ns m axim um am plitude overshoot area vddq vssq maximum amplitude undershoot area time (ns) clock, data strobe and mask overshoot and undershoot definition volts (v)
rev. 0.1 / dec 2008 30 hmt164u6afp(r)6c hmt112u6(7)afp(r)8c hmt125u6(7)afp(r)8c 6.6 pin capacitance parameter symbol ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 units notes min max min max min max min max input/output capacitance (dq, dm, dqs, dqs#, tdqs, tdqs#) c io 1.5 3.0 1.5 3.0 1.5 2.5 tbd tbd pf 1,2,3 input capacitance, ck and ck# c ck tbd 1.6 tbd 1.6 tbd tbd tbd tbd pf 2,3,5 input capacitance delta ck and ck# c dck 0 0.15 0 0.15 tbd tbd tbd tbd pf 2,3,4 input capacitance (all other input-only pins) c i tbd 1.5 tbd 1.5 tbd tbd tbd tbd pf 2,3,6 input capacitance delta, dqs and dqs# c ddqs 0 0.20 0 0.20 tbd tbd tbd tbd pf 2,3,12 input capacitance delta (all ctrl input-only pins) c di_ctrl -0.5 0.3 -0.5 0.3 tbd tbd tbd tbd pf 2,3,7,8 input capacitance delta (all add/cmd input-only pins) c di_add_ cmd -0.5 0.5 -0.5 0.5 tbd tbd tbd tbd pf 2,3,9, 10 input/output capacitance delta (dq, dm, dqs, dqs#) c dio -0.5 0.3 -0.5 0.3 tbd tbd tbd tbd pf 2,3,11 notes: 1. tdqs/tdqs# are not necessarily input function but since tdqs is sharing dm pin and the parasitic characterization of tdqs/tdqs# should be close as much as possible, cio&cdio requirement is applied (recommend deleting note or changing to ?although the dm, tdqs and tdqs# pins have different functions, the loading matches dq and dqs.?) 2. this parameter is not subject to production test. it is verified by design and characterization. input capacitance is measured according to jep147(?procedure for measuring input capacitance using a vector network analyzer(vna)?) with vdd, vddq, vss,vssq applied an d all other pins floating (except the pin under test, cke, reset# and odt as necessary). vdd=vddq=1.5v, vbias=vdd/2 and on-die termination off. 3. this parameter applies to monolithic devices only; stacked/dual-die devices are not covered here 4. absolute value of c ck -c ck #. 5. the minimum c ck will be equal to the minimum c i . 6. input only pins include: odt, cs, cke, a0-a15, ba0-ba2, ras#, cas#, we#. 7. ctrl pins defined as odt, cs and cke. 8. c di_ctrl =c i (cntl) - 0.5 * c i (clk) + c i (clk#)) 9. add pins defined as a0-a15, ba0-ba2 and cmd pins are defined as ras#, cas# and we#. 10. c di_add_cmd =c i (add_cmd) - 0.5*(c i (clk)+c i (clk#)) 11. c dio =c io (dq) - 0.5*(c io (dqs)+c io (dqs#)) 12. absolute value of c io (dqs) - c io (dqs#)
rev. 0.1 / dec 2008 31 hmt164u6afp(r)6c hmt112u6(7)afp(r)8c hmt125u6(7)afp(r)8c 6.7 idd specifications(t case : 0 to 95 o c) 512mb, 64m x 64 u-dimm: hmt164u6afp6c 1gb, 128m x 64 u-dimm: hmt112u6afp8c symbol ddr3 800 ddr3 1066 ddr3 1333 unit note idd0 360 420 480 ma idd1 480 540 580 ma idd2p(f) 100 120 140 ma idd2p(s) 40 40 40 ma idd2q 180 240 280 ma idd2n 200 240 300 ma idd3p 140 180 200 ma idd3n 220 280 340 ma idd4w 700 880 1060 ma idd4r 700 860 1020 ma idd5b 740 780 840 ma idd6(d) 40 40 40 ma 1 idd6(s) 24 24 24 ma 1 idd7 1300 1420 1720 ma symbol ddr3 800 ddr3 1066 ddr3 1333 unit note idd0 640 760 840 ma idd1 760 880 960 ma idd2p(f) 200 240 280 ma idd2p(s) 80 80 80 ma idd2q 360 480 560 ma idd2n 400 480 600 ma idd3p 280 360 400 ma idd3n 440 560 680 ma idd4w 1120 1440 1560 ma idd4r 1040 1320 1680 ma idd5b 1480 1560 1720 ma idd6(d) 80 80 80 ma 1 idd6(s) 48 48 48 ma 1 idd7 1800 2000 2440 ma
rev. 0.1 / dec 2008 32 hmt164u6afp(r)6c hmt112u6(7)afp(r)8c hmt125u6(7)afp(r)8c 1gb, 128m x 72 u-dimm: hmt112u7afp8c 2gb, 256m x 64 u-dimm: hmt125u6afp8c symbol ddr3 800 ddr3 1066 ddr3 1333 unit note idd0 720 855 945 ma idd1 855 990 1080 ma idd2p(f) 225 270 315 ma idd2p(s) 90 90 90 ma idd2q 405 540 630 ma idd2n 450 540 675 ma idd3p 315 405 450 ma idd3n 495 630 765 ma idd4w 1260 1620 1755 ma idd4r 1170 1485 1890 ma idd5b 1665 1755 1935 ma idd6(d) 90 90 90 ma 1 idd6(s) 54 54 54 ma 1 idd7 2025 2250 2745 ma symbol ddr3 800 ddr3 1066 ddr3 1333 unit note idd0 1040 1240 1440 ma idd1 1160 1360 1560 ma idd2p(f) 400 480 560 ma idd2p(s) 160 160 160 ma idd2q 720 960 1120 ma idd2n 800 960 1200 ma idd3p 560 720 800 ma idd3n 880 1120 1360 ma idd4w 1520 1920 2160 ma idd4r 1440 1800 2280 ma idd5b 1880 2040 2320 ma idd6(d) 160 160 160 ma 1 idd6(s) 96 96 96 ma 1 idd7 2200 2480 3040 ma
rev. 0.1 / dec 2008 33 hmt164u6afp(r)6c hmt112u6(7)afp(r)8c hmt125u6(7)afp(r)8c 2gb, 256m x 72 u-dimm: hmt125u7afp8c 6.7 idd measurement conditions within the tables provided furt her down, an overview about the idd measurement conditions is provided as follows: within the tables about idd measurement cond itions, the following definitions are used: - low is defined as vin <= vilac(max.); high is defined as vin >= vihac(min.). - stable is defined as inputs are stable at a high or low level. - floating is defined as inputs are vref = vddq / 2. - switching is defined as described in the following 2 tables. symbol ddr3 800 ddr3 1066 ddr3 1333 unit note idd0 1170 1395 1620 ma idd1 1305 1530 1755 ma idd2p(f) 450 540 630 ma idd2p(s) 180 180 180 ma idd2q 810 1080 1260 ma idd2n 900 1080 1350 ma idd3p 630 810 900 ma idd3n 990 1260 1530 ma idd4w 1710 2160 2430 ma idd4r 1620 2025 2565 ma idd5b 2115 2295 2610 ma idd6(d) 180 180 180 ma 1 idd6(s) 108 108 108 ma 1 idd7 2475 2790 3420 ma table 1 ? overview of tables providing idd measurement conditions and dram behavior table number measurement conditions table 5 on page 33 idd0 and idd1 table 6 on page 36 idd2n, idd2q, idd2p(0), idd2p(1) table 7 on page 38 idd3n and idd3p table 8 on page 39 idd4r, idd4w, idd7 table 9 on page 42 idd7 for different speed grades and different trrd, tfaw conditions table 10 on page 43 idd5b table 11 on page 44 idd6, idd6et
rev. 0.1 / dec 2008 34 hmt164u6afp(r)6c hmt112u6(7)afp(r)8c hmt125u6(7)afp(r)8c table 2 ? definition of switching for address and command input signals switching for address (row, column) and command signals (cs , ras , cas , we ) is defined as: address (row, column) : if not otherwise mentioned the inputs are stable at high or low during 4 clocks and change then to the opposite value (e.g. ax ax ax ax ax ax ax ax ax ax ax ax..... please see each iddx definition for details bank address : if not otherwise mentioned the bank addresse s should be switched like the row/column addresses - please see each iddx definition for details command (cs , ras , cas , we ): define d = {cs , ras , cas , we }:= {high, low, low, low} define d = {cs , ras , cas , we }:= {high, high,high,high} define command background pattern = d d d d d d d d d d d d ... if other commands are necessary (e.g. act for idd0 or read for idd4r), the background pattern command is substitu ted by the respective cs , ras , cas , we levels of the necessary command. see each iddx definition for details and figures 1,2,3 as examples. table 3 ? definition of switching for data (dq) switching for data (dq) is defined as data (dq) data dq is changing between high and low every other data transfer (once per clock) for dq signals, which means that data dq is stable during one clock; see each iddx definition for exceptions from this rule and for further details. see figures 1,2,3 as examples. data masking (dm) no switching; dm must be driven low all the time
rev. 0.1 / dec 2008 35 hmt164u6afp(r)6c hmt112u6(7)afp(r)8c hmt125u6(7)afp(r)8c timing parameters are listed in the following table: the following conditions apply: - idd specifications are tested after the device is properly initialized. - input slew rate is specified by ac parametric test conditions. - idd parameters are specified with odt an d output buffer disabled (mr1 bit a12). table 4 ? for idd testing the fo llowing parameters are utilized. parameter bin ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 unit 5-5-5 6-6-6 6-6-6 7-7-7 8-8-8 7-7-7 8-8-8 9-9-9 8-8-8 9-9-9 101010 t ckmin (idd) 2.5 1.875 1.5 1.25 ns cl(idd) 566787898910clk t rcdmin (idd) 12.5 15 11.25 13.13 15 10.5 12 13.5 10 11.25 12.5 ns t rcmin (idd) 50 52.5 48.75 50.63 52. 50 46.5 48 49.5 tbd tbd tbd ns t rasmin (idd) 37.5 37.5 37.5 37.5 37.5 36 36 36 tbd tbd tbd ns t rpmin (idd) 12.5 15 11.25 13.13 15 10.5 12 13.5 10 11.25 12.5 ns t faw (idd) x4/ x8 40 40 37.5 37.5 37.5 30 30 30 30 30 30 ns x1650505050504545454040 40ns t rrd (idd) x4/ x8 10 10 7.5 7.5 7.5 6.0 6.0 6.0 6.0 6.0 6.0 ns x1610101010107.57.57.57.57.57.5ns t rfc (idd) - 512mb 90 90 90 90 90 90 90 90 90 90 90 ns t rfc (idd) - 1 gb 110 110 110 110 110 110 110 110 110 110 110 ns t rfc (idd) - 2 gb 160 160 160 160 160 160 160 160 160 160 160 ns t rfc (idd) - 4 gb tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ns
rev. 0.1 / dec 2008 36 hmt164u6afp(r)6c hmt112u6(7)afp(r)8c hmt125u6(7)afp(r)8c table 5 ? idd measurement conditions for idd0 and idd1 current i dd0 i dd1 name operating current 0 -> one bank activate -> precharge operating current 1 -> one bank activate -> read -> precharge measurement condition timing diagram example figure 1 cke high high external clock on on t ck t ckmin (idd) t ckmin (idd) t rc t rcmin (idd) t rcmin (idd) t ras t rasmin (idd) t rasmin (idd) t rcd n.a. t rcdmin (idd) t rrd n.a. n.a. cl n.a. cl(idd) al n.a. 0 cs high between. activate and precharge commands high between activate, read and precharge command inputs (cs ,ras , cas , we ) switching as described in table 2 only exceptions are activate and precharge commands; example of idd0 pattern: a0 ddd dddd dddd ddd p0 (ddr3-800: t ras = 37.5ns between (a)ctivate and (p)recharge to bank 0; definition of d and d : see table 2 switching as described in table 2; only exceptions are activate, read and precharge commands; example of idd1 pattern: a0 ddd d r0 dd dddd ddd p0 (ddr3-800 -555: t rcd = 12.5ns between (a)ctivate and (r)ead to bank 0 ; definition of d and d : see table 2)
rev. 0.1 / dec 2008 37 hmt164u6afp(r)6c hmt112u6(7)afp(r)8c hmt125u6(7)afp(r)8c row, column addresses row addresses switching as described in table 2; address input a10 must be low all the time! row addresses switching as described in table 2; address input a10 must be low all the time! bank addresses bank address is fixed (bank 0) bank address is fixed (bank 0) data i/o switching as described in table 3 read data: output data switches every clock, which means that read data is stable during one clock cycle. to achieve iout = 0ma, the output buffer should be switched off by mr1 bit a12 set to ?1?. when there is no read data burst from dram, the dq i/o should be floating. output buffer dq,dqs / mr1 bit a12 off / 1 off / 1 odt / mr1 bits [a6, a2] disabled / [0,0] disabled / [0,0] burst length n.a. 8 fixed / mr0 bits [a1, a0] = {0,0} active banks one act-pre loop one act-rd-pre loop idle banks all other all other precharge power down mode / mode register bit 12 n.a. n.a. table 5 ? idd measurement conditions for idd0 and idd1 current i dd0 i dd1 name operating current 0 -> one bank activate -> precharge operating current 1 -> one bank activate -> read -> precharge
rev. 0.1 / dec 2008 38 hmt164u6afp(r)6c hmt112u6(7)afp(r)8c hmt125u6(7)afp(r)8c < figure 1. idd1 example > (ddr3-800-555, 512mb x8): data dq is shown but the output buffer should be switched off (per mr1 bit a12 =?1?) to ac hieve iout = 0ma. address inputs are split into 3 parts. t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t12 t14 t16 t18 3ff 000 3ff 000 3f 000 000 11 00 11 00 00 act d# d d# rd d d# d# d d d# d# d d d# pre d d d# 0 0 1 1 0 0 1 1 ck ba[2:0] addr_a[9:0] addr_b[10] addr_c[12:11] cs ras cas we cmd dq dm idd1 measurment loop a. in ddr3, the mrs bit 12 defines dll on/off behaviou r only for precharge power down. there are 2 different precharge power down states possible: one with dll on (fast exit, bit 12 = 1) and one with dll off (slow exit, bit 12 = 0). b. because it is an exit after precharge power down, the valid commands are: activate, refresh, mode-register set, enter - self refresh
rev. 0.1 / dec 2008 39 hmt164u6afp(r)6c hmt112u6(7)afp(r)8c hmt125u6(7)afp(r)8c table 6 ? idd measurement conditions for idd2n, idd2p(1), idd2p(0) and idd2q current i dd2n i dd2p (1) a a. i dd2p (0) i dd2q name precharge standby current precharge power down current fast exit - mrs a12 bit = 1 precharge power down current slow exit - mrs a12 bit = 0 precharge quiet standby current measurement condition timing diagram example figure 2 cke high low low high external clockonononon t ck t ckmin (idd) t ckmin (idd) t ckmin (idd) t ckmin (idd) t rc n.a. n.a. n.a. n.a. t ras n.a. n.a. n.a. n.a. t rcd n.a. n.a. n.a. n.a. t rrd n.a. n.a. n.a. n.a. cl n.a. n.a. n.a. n.a. al n.a. n.a. n.a. n.a. cs high stable stable high bank address, row addr. and command inputs switching as described in table 2 stable stable stable data inputs switching floating floating floating output buffer dq,dqs / mr1 bit a12 off / 1 off / 1 off / 1 off / 1 odt / mr1 bits [a6, a2] disabled / [0,0] disabled / [0,0] disabled / [0,0] disabled / [0,0] burst length n.a. n.a. n.a. n.a. active banks none none none none idle banks all all all all precharge power down mode / mode register bit a n.a. fast exit / 1 (any valid command after txp b ) b. slow exit / 0 slow exit (rd and odt commands must satisfy txpdll-al) n.a.
rev. 0.1 / dec 2008 40 hmt164u6afp(r)6c hmt112u6(7)afp(r)8c hmt125u6(7)afp(r)8c (ddr3-800-555, 512mb x8) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 7 0 0 7 0 0 d# d# d d d# d# d d d# d# ff 00 00 ff ff 00 00 ff ff 00 00 ff ff 00 00 ff ff 00 00 ff ff ck ba[2:0] addr[12:0] cs ras cas we cmd dq[7:0] dm
rev. 0.1 / dec 2008 41 hmt164u6afp(r)6c hmt112u6(7)afp(r)8c hmt125u6(7)afp(r)8c table 7 ? i dd measurement conditions fo r idd3n and idd3p(fast exit) current i dd3n i dd3p name active standby current active power-down current a always fast exit a. ddr3 will offer only one active power down mode with dll on (-> fast exit). mrs bit 12 will not be used for active power down. instead bit 12 will be used to sw itch between two different precharge power down modes. measurement condition timing diagram example figure 2 cke high low external clock on on t ck t ckmin (idd) t ckmin (idd) t rc n.a. n.a. t ras n.a. n.a. t rcd n.a. n.a. t rrd n.a. n.a. cl n.a. n.a. al n.a. n.a. cs high stable addr. and cmd inputs switching as described in table 2 stable data inputs switching as described in table 3 floating output buffer dq,dqs / mr1 bit a12 off / 1 off / 1 odt / mr1 bits [a6, a2] disabled / [0,0] disabled / [0,0] burst length n.a. n.a. active banks all all idle banks none none precharge power down mode / mode register bit a n.a. n.a. (active power down mode is always ?fast exit? with dll on
rev. 0.1 / dec 2008 42 hmt164u6afp(r)6c hmt112u6(7)afp(r)8c hmt125u6(7)afp(r)8c table 8 ? idd measurement conditions for idd4r, idd4w and idd7 current i dd4r i dd4w i dd7 name operating current burst read operating current burst write all bank interleave read current measurement condition timing diagram example figure 3 cke high high high external clock on on on t ck t ckmin (idd) t ckmin (idd) t ckmin (idd) t rc n.a. n.a. t rcmin (idd) t ras n.a. n.a. t rasmin (idd) t rcd n.a. n.a. t rcdmin (idd) t rrd n.a. n.a. t rrdmin (idd) cl cl(idd) cl(idd) cl(idd) al 0 0 t rcdmin - 1 t ck cs high btw. valid cmds high btw. valid cmds high btw. valid cmds command inputs (cs , ras , cas , we ) switching as described in table 2; exceptions are read commands => idd4r pattern: r0 ddd r1 ddd r2 ddd r3 .dd d r4 ..... rx = read from bank x; definition of d and d : see table 2 switching as described in table 2; exceptions are write commands => idd4w pattern: w0 ddd w1 ddd w2 ddd w3 ddd w4 ... wx = write to bank x; definition of d and d : see table 2 for patterns see table 9
rev. 0.1 / dec 2008 43 hmt164u6afp(r)6c hmt112u6(7)afp(r)8c hmt125u6(7)afp(r)8c row, column addresses column addresses switching as described in table 2; address input a10 must be low all the time! column addresses switching as described in table 2; address input a10 must be low all the time! stable during deselects bank addresses bank address cycling (0 -> 1 - > 2 -> 3...) bank address cycling (0 -> 1 - > 2 -> 3...) bank address cycling (0 -> 1 - > 2 -> 3...), see pattern in table 9 dq i/o seamless read data burst (bl8): output data switches every clock, which means that read data is stable during one clock cycle. to achieve iout = 0ma the output buffer should be switched off by mr1 bit a12 set to ?1?. seamless write data burst (bl8): input data switches every clock, wh ich means that write data is stable during one clock cycle. dm is low all the time. read data (bl8): output data switches every clock, which means that read data is stable during one clock cycle. to achieve iout = 0ma the output buffer should be switched off by mr1 bit a12 set to ?1?. output buffer dq,dqs / mr1 bit a12 off / 1 off / 1 off / 1 odt / mr1 bits [a6, a2] disabled / [0,0] disabled / [0,0] disabled / [0,0] burst length 8 fixed / mr0 bits [a1, a0] = {0,0} 8 fixed / mr0 bits [a1, a0] = {0,0} 8 fixed / mr0 bits [a1, a0] = {0,0} active banks all all all, rotational idle banks none none none precharge power down mode / mode register bit n.a. n.a. n.a. table 8 ? idd measurement conditions for idd4r, idd4w and idd7 current i dd4r i dd4w i dd7 name operating current burst read operating current burst write all bank interleave read current
rev. 0.1 / dec 2008 44 hmt164u6afp(r)6c hmt112u6(7)afp(r)8c hmt125u6(7)afp(r)8c < figure 3. idd4r example > (ddr3-800-555, 512mb x8): data dq is shown but the output buffer should be switched off (per mr1 bi t a12=?1?) to achieve iout = 0ma. address inputs are split into 3 parts. 001 010 011 00 00 ff ff 00 00 ff ff 00 00 ff ff 00 00 ff ff ck ba[2:0] addr[12:0] cs ras cas we cmd[2:0] dq[7:0] dm 3ff 000 3ff addr_b[10] 11 00 11 addr_c[12:11] 000 000 00 rd d d# d# rd d d# d# d# rd d# rd d -> start of measurement loop
rev. 0.1 / dec 2008 45 hmt164u6afp(r)6c hmt112u6(7)afp(r)8c hmt125u6(7)afp(r)8c table 9 ? idd7 pattern for different speed grades and different trrd, tfaw conditions speed bin org. tfaw tfaw trrd trrd idd7 pattern a a. a0 = activation of bank 0; ra0 = read with auto-precharge of bank 0; d = deselect mb/s [ns] [clk] [ns] [clk] (note this entire sequence is repeated.) 800 all x4/x8 40 16 10 4 a0 ra0 d d a1 ra1 d d a2 ra2 d d a3 ra3 d d a4 ra4 d d a5 ra5 d d a6 ra6 d d a7 ra7 d d all x16 50 20 10 4 a0 ra0 d d a1 ra1 d d a2 ra2 d d a3 ra3 d d d d d d a4 ra4 d d a5 ra5 d d a6 ra6 d d a7 ra7 d d d d d d 1066 all x4/x8 37.5 20 7.5 4 a0 ra0 d d a1 ra1 d d a2 ra2 d d a3 ra3 d d d d d d a4 ra4 d d a5 ra5 d d a6 ra6 d d a7 ra7 d d d d d d all x16 50 27 10 6 a0 ra0 d d d d a1 ra1 d d d d a2 ra2 d d d d a3 ra3 d d d d d d d a4 ra4 d d d d a5 ra5 d d d d a6 ra6 d d d d a7 ra7 d d d d d d d 1333 all x4/x8 30 20 6 4 a0 ra0 d d a1 ra1 d d a2 ra2 d d a3 ra3 d d d d d d a4 ra4 d d a5 ra5 d d a6 ra6 d d a7 ra7 d d d d d d all x16 45 30 7.5 5 a0 ra0 d d d a1 ra1 d d d a2 ra2 d d d a3 ra3 d d d d d d d d d d d d d a4 ra4 d d d a5 ra5 d d d a6 ra6 d d d a7 ra7 d d d d d d d d d d d d d 1600 all x4/x8 30 24 6 5 a0 ra0 d d d a1 ra1 d d d a2 ra2 d d d a3 ra3 d d d d d d d a4 ra4 d d d a5 ra5 d d d a6 ra6 d d d a7 ra7 d d d d d d d all x16 40 32 7.5 6 a0 ra0 d d d d a1 ra1 d d d d a2 ra2 d d d d a3 ra3 d d d d d d d d d d d d a4 ra4 d d d d a5 ra5 d d d d a6 ra6 d d d d a7 ra7 d d d d d d d d d d d d
rev. 0.1 / dec 2008 46 hmt164u6afp(r)6c hmt112u6(7)afp(r)8c hmt125u6(7)afp(r)8c table 10 ? idd measuremen t conditions for idd5b current i dd5b name burst refresh current measurement condition cke high external clock on t ck t ckmin (idd) t rc n.a. t ras n.a. t rcd n.a. t rrd n.a. t rfc t rfcmin (idd) cl n.a. al n.a. cs high btw. valid cmds addr. and cmd inputs switching data inputs switching output buffer dq,dqs / mr1 bit a12 off / 1 odt / mr1 bits [a6, a2] disabled / [0,0] burst length n.a. active banks refresh command every trfc=trfcmin idle banks none precharge power down mode / mode register bit n.a.
rev. 0.1 / dec 2008 47 hmt164u6afp(r)6c hmt112u6(7)afp(r)8c hmt125u6(7)afp(r)8c table 11 ? idd measurement co nditions for idd6 and idd6et current i dd6 i dd6et name self-refresh current normal temperature range t case = 0. 85 c self-refresh current extended temperature range a t case = 0. 95 c a. users should refer to the dram supplier data sheet and/or the dimm spd to determine if ddr3 sdram devices support the following options or requirements referred to in this material. measurement condition temperature t case = 85 c t case = 95 c auto self refresh (asr) / mr2 bit a6 disabled / ?0? disabled / ?0? self refresh temperature range (srt) / mr2 bit a7 normal / ?0? extended / ?1? cke low low external clock off; ck and ck at low off; ck and ck at low t ck n.a. n.a. t rc n.a. n.a. t ras n.a. n.a. t rcd n.a. n.a. t rrd n.a. n.a. cl n.a. n.a. al n.a. n.a. cs floating floating command inputs (ras , cas , we ) floating floating row, column addresses floating floating bank addresses floating floating data i/o floating floating output buffer dq,dqs / mr1 bit a12 off / 1 off / 1 odt / mr1 bits [a6, a2] disabled / [0,0] disabled / [0,0] burst length n.a. n.a. active banks all during self-refresh ac tions all during self-refresh actions idle banks all btw. self-refresh actions all btw. self-refresh actions precharge power down mode / mr0 bit a12 n.a. n.a.
rev. 0.1 / dec 2008 48 hmt164u6afp(r)6c hmt112u6(7)afp(r)8c hmt125u6(7)afp(r)8c 7. electrical characteristics and ac timing 7.1 refresh parameters by device density 7.2 ddr3 sdram standard speed bins includ e tck, trcd, trp, tr as and trc for each corresponding bin parameter symbol 512mb 1gb 2gb 4gb 8gb units ref command to act or ref command time trfc 90 110 160 300 350 ns average periodic refresh interval trefi 0 c < t case < 85 c 7.8 7.8 7.8 7.8 7.8 ms 85 c < t case < 95 c 3.9 3.9 3.9 3.9 3.9 ms ddr3 800 speed bin ddr3-800d ddr3-800e unit notes cl - nrcd - nrp 5-5-5 6-6-6 parameter symbol min max min max internal read command to first data t aa 12.5201520ns act to internal read or write delay time t rcd 12.5 ? 15 ? ns pre command period t rp 12.5 ? 15 ? ns act to act or ref command period t rc 50 ? 52.5 ? ns act to pre command period t ras 37.5 9 * trefi 37.5 9 * trefi ns cl = 5 cwl = 5 t ck(avg) 2.5 3.3 reserved ns 1)2)3)4) cl = 6 cwl = 5 t ck(avg) 2.5 3.3 2.5 3.3 ns 1)2)3) supported cl settings 5, 6 6 n ck supported cwl settings 55 n ck
rev. 0.1 / dec 2008 49 hmt164u6afp(r)6c hmt112u6(7)afp(r)8c hmt125u6(7)afp(r)8c ddr3 1066 speed bin ddr3-1066e ddr3-1066f ddr3-1066g unit note cl - nrcd - nrp 6-6-6 7-7-7 8-8-8 parameter symbol min max min max min max internal read command to first data t aa 11.25 20 13.125 20 15 20 ns act to internal read or write delay time t rcd 11.25 ? 13.125 ? 15 ? ns pre command period t rp 11.25 ? 13.125 ? 15 ? ns act to act or ref command period t rc 48.75 ? 50.625 ? 52.5 ? ns act to pre command period t ras 37.5 9 * trefi 37.5 9 * trefi 37.5 9 * trefi ns cl = 5 cwl = 5 t ck(avg) 2.5 3.3 reserved reserved ns 1)2)3)4)6) cwl = 6 t ck(avg) reserved reserved reserved ns 4) cl = 6 cwl = 5 t ck(avg) 2.5 3.3 2.5 3.3 2.5 3.3 ns 1)2)3)6) cwl = 6 t ck(avg) 1.875 < 2.5 reserved reserved ns 1)2)3)4) cl = 7 cwl = 5 t ck(avg) reserved reserved reserved ns 4) cwl = 6 t ck(avg) 1.875 < 2.5 1.875 < 2.5 reserved ns 1)2)3)4) cl = 8 cwl = 5 t ck(avg) reserved reserved reserved ns 4) cwl = 6 t ck(avg) 1.875 < 2.5 1.875 < 2.5 1.875 < 2.5 ns 1)2)3) supported cl settings 5, 6, 7, 8 6, 7, 8 6, 8 n ck supported cwl settings 5, 6 5, 6 5, 6 n ck
rev. 0.1 / dec 2008 50 hmt164u6afp(r)6c hmt112u6(7)afp(r)8c hmt125u6(7)afp(r)8c ddr3 1333 speed bin ddr3-1333f (optional) ddr3-1333g ddr3-1333h ddr3-1333j (optional) unit note cl - nrcd - nrp 7-7-7 8-8-8 9-9-9 10-10-10 parameter symbol min max min max min max min max internal read command to first t aa 10.5 20 12 20 13.5 20 15 20 ns act to internal read or write delay time t rcd 10.5 ? 12 ? 13.5 ? 15 ? ns pre command period t rp 10.5 ? 12 ? 13.5 ? 15 ? ns act to act or ref command period t rc 46.5 ? 48 ? 49.5 ? 51 ? ns act to pre command period t ras 36 9 * trefi 36 9 * trefi 36 9 * trefi 36 9 * trefi ns cl = 5 cwl = 5 t ck(avg) 2.5 3.3 2.5 3.3 reserved reserved ns 1,2,3,4,7 cwl = 6, 7 t ck(avg) reserved reserved reserved reserved ns 4 cl = 6 cwl = 5 t ck(avg) 2.5 3.3 2.5 3.3 2.5 3.3 2.5 3.3 ns 1,2,3,7 cwl = 6 t ck(avg) 1.875 < 2.5 reserved reserved reserved ns 1,2,3,4,7 cwl = 7 t ck(avg) reserved reserved reserved reserved ns 4 cl = 7 cwl = 5 t ck(avg) reserved reserved reserved reserved ns 4 cwl = 6 t ck(avg) 1.875 < 2.5 1.875 < 2.5 reserved reserved ns 1,2,3,4,7 cwl = 7 t ck(avg) 1.5 <1.875 reserved reserved reserved ns 1,2,3,4 cl = 8 cwl = 5 t ck(avg) reserved reserved reserved reserved ns 4 cwl = 6 t ck(avg) 1.875 < 2.5 1.875 < 2.5 1.875 < 2.5 1.875 < 2.5 ns 1,2,3,7 cwl = 7 t ck(avg) 1.5 <1.875 1.5 <1.875 reserved reserved ns 1,2,3,4 cl = 9 cwl = 5, 6 t ck(avg) reserved reserved reserved reserved ns 4 cwl = 7 t ck(avg) 1.5 <1.875 1.5 <1.875 1.5 <1.875 reserved ns 1,2,3,4 cl = 10 cwl = 5, 6 t ck(avg) reserved reserved reserved reserved ns 4 cwl = 7 t ck(avg) 1.5 <1.875 1.5 <1.875 1.5 <1.875 1.5 <1.875 ns 1,2,3 (optional) (optional) (optional) ns 5 supported cl settings 5, 6, 7, 8, 9 5, 6, 7, 8, 9 6, 8, 9 6, 8, 10 n ck supported cwl settings 5, 6, 7 5, 6, 7 5, 6, 7 5, 6, 7 n ck
rev. 0.1 / dec 2008 51 hmt164u6afp(r)6c hmt112u6(7)afp(r)8c hmt125u6(7)afp(r)8c ddr3 1600 speed bin ddr3-1600g (optional) ddr3-1600h ddr3-1600j ddr3-1600k (optional) unit note cl - nrcd - nrp 8-8-8 9-9-9 10-10-10 11-11-11 parameter symbol min max min max min max min max internal read command to first data t aa 10 20 11.25 20 12.5 20 13.75 20 ns act to internal read or write delay time t rcd 10 ? 11.25 ? 12.5 ? 13.75 ? ns pre command period t rp 10 ? 11.25 ? 12.5 ? 13.75 ? ns act to act or ref command period t rc 45 ? 46.25 ? 47.5 ? 48.75 ? ns act to pre command period t ras 35 9 * trefi 35 9 * trefi 35 9 * trefi 35 9 * trefi ns cl = 5 cwl = 5 t ck(avg) 2.5 3.3 2.5 3.3 2.5 3.3 reserved ns 1,2,3,4,8 cwl = 6, 7, 8 t ck(avg) reserved reserved reserved reserved ns 4 cl = 6 cwl = 5 t ck(avg) 2.5 3.3 2.5 3.3 2.5 3.3 2.5 3.3 ns 1,2,3,8 cwl = 6 t ck(avg) 1.875 < 2.5 1.875 < 2.5 reserved reserved ns 1,2,3,4,8 cwl = 7, 8 t ck(avg) reserved reserved reserved reserved ns 4 cl = 7 cwl = 5 t ck(avg) reserved reserved reserved reserved ns 4 cwl = 6 t ck(avg) 1.875 < 2.5 1.875 < 2.5 1.875 < 2.5 reserved ns 1,2,3,4,8 cwl = 7 t ck(avg) 1.5 <1.875 reserved reserved reserved ns 1,2,3,4,8 cwl = 8 t ck(avg) reserved reserved reserved reserved ns 4 cl = 8 cwl = 5 t ck(avg) reserved reserved reserved reserved ns 4 cwl = 6 t ck(avg) 1.875 < 2.5 1.875 < 2.5 1.875 < 2.5 1.875 < 2.5 ns 1,2,3,8 cwl = 7 t ck(avg) 1.5 <1.875 1.5 <1.875 reserved reserved ns 1,2,3,4,8 cwl = 8 t ck(avg) 1.25 < 1.5 reserved reserved reserved ns 1,2,3,4 cl = 9 cwl = 5, 6 t ck(avg) reserved reserved reserved reserved ns 4 cwl = 7 t ck(avg) 1.5 <1.875 1.5 <1.875 1.5 <1.875 reserved ns 1,2,3,4,8 cwl = 8 t ck(avg) 1.25 < 1.5 1.25 < 1.5 reserved reserved ns 1,2,3,4 cl = 10 cwl = 5, 6 t ck(avg) reserved reserved reserved reserved ns 4 cwl = 7 t ck(avg) 1.5 <1.875 1.5 <1.875 1.5 <1.875 1.5 <1.875 ns 1,2,3,8 cwl = 8 t ck(avg) 1.25 < 1.5 1.25 < 1.5 1.25 < 1.5 reserved ns 1,2,3,4
rev. 0.1 / dec 2008 52 hmt164u6afp(r)6c hmt112u6(7)afp(r)8c hmt125u6(7)afp(r)8c *speed bin table notes * absolute specification (t oper ; v ddq = v dd = 1.5v +/- 0.075 v); notes: 1. the cl setting and cwl setting result in tck(avg).min and tck(avg).max requirements. when making a selection of tck(avg), both need to be fulfilled: requirements from cl setting as well as requirements from cwl setting. 2. tck(avg).min limits: since cas latency is not purely an alog - data and strobe output are synchronized by the dll - all possible intermediate frequencies may not be gu aranteed. an application should use the next smaller jedec standard tck(avg) value (2.5, 1.875, 1.5, or 1.25 ns ) when calculating cl [nck] = taa [ns] / tck(avg) [ns], rounding up to the next ?supported cl?. 3. tck(avg).max limits: calculate tck(avg) = taa.max / cl selected and round the result ing tck(avg) down to the next valid speed bin (i.e. 3.3ns or 2.5ns or 1.875 ns or 1.25 ns). this result is tck(avg).max corresponding to clselected. 4. ?reserved? settings are not allowed. user must program a different value. 5. ?optional? settings allow certain devices in the industry to support this setting, however, it is not a mandatory feature. refer to supplier?s data sheet and sp d information if and how this setting is supported. 6. any ddr3-1066 speed bin also supports functional operat ion at lower frequencies as shown in the table which are not subject to production tests but verified by design/characterization. 7. any ddr3-1333 speed bin also supports functional operat ion at lower frequencies as shown in the table which are not subject to production tests but verified by design/characterization. 8. any ddr3-1600 speed bin also supports functional operat ion at lower frequencies as shown in the table which are not subject to production tests but verified by design/characterization. cl = 11 cwl = 5, 6, 7 t ck(avg) reserved reserved reserved reserved ns 4 cwl = 8 t ck(avg) 1.25 < 1.5 1.25 < 1.5 1.25 < 1.5 1.25 < 1.5 ns 1,2,3 (optional) (optional) (optional) ns 5 supported cl settings 5, 6, 7, 8, 9, 10 5, 6, 7, 8, 9, 10 5, 6, 7, 8, 9, 10 6, 8, 10, 11 n ck supported cwl settings 5, 6, 7, 8 5 , 6, 7, 8 5, 6, 7, 8 5, 6, 7, 8 n ck
rev. 0.1 / dec 2008 53 hmt164u6afp(r)6c hmt112u6(7)afp(r)8c hmt125u6(7)afp(r)8c 8. dimm outline diagram 8.1 164mx64 - hm t164u6afp(r)6c 9.50 30.00 17.30 max r0.70 2 x 2.50 0.10 min 1.45 detail-a detail-b 2.10 0.15 4 x 3.00 0.10 2 x 2.30 0.10 5.175 47.00 71.00 128.95 133.35 0.35 1.00 0.3~1.0 detail - b 5.00 3.80 0.05 2.50 0.20 0.80 0.05 0.3 0.15 2.50 full r detail - a 1.27 ? 0.10 3.18 front back side spd note) all dimensions are in millimeters unless otherwise stated.
rev. 0.1 / dec 2008 54 hmt164u6afp(r)6c hmt112u6(7)afp(r)8c hmt125u6(7)afp(r)8c 8.2 128mx64 - hm t112u6afp(r)8c 9.50 17.30 max r0.70 2 x 2.50 0.10 min 1.45 detail-a detail-b 2.10 0.15 4 x 3.00 0.10 2 x 2.30 0.10 5.175 47.00 71.00 128.95 133.35 0.35 1.00 0.3~1.0 detail - b 5.00 3.80 0.05 2.50 0.20 0.80 0.05 0.3 0.15 2.50 full r detail - a 1.27 ? 0.10 3.18 back side 30.00 front spd note) all dimensions are in milli meters unless otherwise stated.
rev. 0.1 / dec 2008 55 hmt164u6afp(r)6c hmt112u6(7)afp(r)8c hmt125u6(7)afp(r)8c 8.3 128mx72 - hm t112u7afp(r)8c 9.50 17.30 max r0.70 2 x 2.50 0.10 min 1.45 detail-a detail-b 2.10 0.15 4 x 3.00 0.10 2 x 2.30 0.10 5.175 47.00 71.00 128.95 133.35 0.35 1.00 0.3~1.0 detail - b 5.00 3.80 0.05 2.50 0.20 0.80 0.05 0.3 0.15 2.50 full r detail - a 1.27 ? 0.10 3.18 back side 30.00 front spd note) all dimensions are in millimeters unless otherwise stated.
rev. 0.1 / dec 2008 56 hmt164u6afp(r)6c hmt112u6(7)afp(r)8c hmt125u6(7)afp(r)8c 8.4 256mx64 - hm t125u6afp(r)8c 9.50 17.30 max r0.70 2 x 2.50 0.10 min 1.45 detail-a detail-b 2.10 0.15 4 x 3.00 0.10 2 x 2.30 0.10 5.175 47.00 71.00 128.95 133.35 0.35 1.00 0.3~1.0 detail - b 5.00 3.80 0.05 2.50 0.20 0.80 0.05 0.3 0.15 2.50 full r detail - a 1.27 ? 0.10 4.00 back side 30.00 front spd note) all dimensions are in milli meters unless otherwise stated.
rev. 0.1 / dec 2008 57 hmt164u6afp(r)6c hmt112u6(7)afp(r)8c hmt125u6(7)afp(r)8c 8.5 256mx72 - hm t125u7afp(r)8c 9.50 17.30 max r0.70 2 x 2.50 0.10 min 1.45 detail-a detail-b 2.10 0.15 4 x 3.00 0.10 2 x 2.30 0.10 5.175 47.00 71.00 128.95 133.35 0.35 1.00 0.3~1.0 detail - b 5.00 3.80 0.05 2.50 0.20 0.80 0.05 0.3 0.15 2.50 full r detail - a 1.27 ? 0.10 4.00 back side 30.00 front spd note) all dimensions are in millimeters unl ess otherwise stated.
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